Among non-volatile memories, MRAM (Magnetoresistive Random Access Memory) using changes in magnetoresistance is a possible RAM capable of high-speed operation and programmable/erasable for unlimited programming/erasing cycles in practice. An existing cell configuration of MRAM includes one magnetic tunnel junction element TMR, a select transistor MCT for read, a program word line WWL, a bit line BL, and a source line SL. As illustrated in FIG. 34, the magnetic tunnel junction element TMR has at least two magnetic layers, one of them being a fixed layer PL having a fixed spin direction and the other being a free layer FL having two states of spin directions of a parallel direction to the fixed layer and an anti-parallel direction to the fixed layer. A tunnel barrier film TB is provided between these layers. Storage of information is achieved by a direction of spin of the free layer, and an electric resistance of the magnetic tunnel junction element TMR is in a high-resistance state in the anti-parallel state and is in a low-resistance state in the parallel state. In a read operation, magnitude of a resistance of the magnetic tunnel junction element TMR is read. Meanwhile, in a programming/erasing operation, current is flowed in the program word line WWL and the bit line BL and directions of spin of the free layer is controlled by a resultant induced magnetic field in the magnetic tunnel junction element TMR upon flowing the current. However, in this programming/erasing method, since the size of the magnetic field necessary for programming/erasing is increased as the magnetic tunnel junction element TMR is miniaturized, there is a problem of an increase in current to be flowed in the program word line and bit line. Regarding this problem, there is a spin-injection RAM or SPRAM (Spin-Transfer Torque RAM) utilizing the spin-injection magnetization inversion technology changing directions of spin in the free layer by perpendicularly flowing current in the magnetic tunnel junction element TMR as introduced by Non-Patent Document 1 (2005 International Electron Device Meeting, Technical Digest Papers, pp. 459-462). As illustrated in FIG. 35, this programming/erasing method can control directions of spin in a free layer by current in a direction perpendicular to the fixed layer PL, the tunnel barrier film TB, and the free layer FL. In a memory chip, a bit line and a source line are provided, a select transistor and a magnetic tunnel junction element TMR are arranged between the bit line and the source line, and current is flowed from the bit line to the source line or from the source line to the bit line to perform programming and erasing. As the current required for programming/erasing is proportional to magnitude of the magnetic tunnel junction element TMR, the programming/erasing current can be reduced along with miniaturization of the magnetic tunnel junction element TMR, and it is excellent in scalability. As the tunnel barrier film TB, MgO is used.